clock_verilog

First Project for STRUCTURED DESIGN OF INTEGRATED CIRCUITS discipline at UFPB. 24h clock with verilog

Funcionalidade: relógio digital
Entradas: sinal de clock de 50MHz, reset
Saídas: 6 x 7 saídas (6 displays de 7 segment

https://sig-arq.ufpb.br/arquivos/20232200390b125557224d341662704c1/Metodologia_Top_Down_e_Projeto_01.pptx.pdf

Part 2 - Functional verification (Modelsim)

Relatório: https://docs.google.com/document/d/1gQbyc7YqgM2i0S7PUEcjjVg20sU4GWhu3YzOx_Y2t1c/edit?usp=sharing

Testbench implementation

Modelsim screenshot

Docs:

OBS: There is a known error at modelsim simulation.

For some reason, the first "run -all" detects a bug.
Just click at continue to continue the expected simulation